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A COMPARATIVE STUDY OF FULL ADDER USING STATIC CMOS LOGIC STYLE

Downloads: 4,808 Avg Rating: 0.00 By: Ms Manisha Kundu in 2014.
In this paper 1-bit CMOS full adder cells are studied using standard static CMOS logic style. The comparison is carried out using several parameters like number of transistors, delay, power dissipation and power delay product (PDP).The circuits are designed at transistor level using 180nm CMOS technology. Different full adders are studied in this paper like Conventional CMOS (C-CMOS), Complementary pass transistor logic (CPL), Double pass transistor logic (DPL), Transmission gate (TGA), Transmission function (TFA), New 14T, Hybrid CMOS, HPSC, Pseudo nMOS, GDI full adders.

Additional Authors: MANISHA, ARCHANA

Document Type: Report Topic Area: Other Submitted: 23rd Jun 2014
Institution: DCRUST MURTHAL HARYANA INDIA Department: ELECTRONICS AND COMMUNICATION ENGINEERING Country: India
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